1. Field of the Invention
The present invention relates to a semiconductor memory. It is particularly related to a miniaturized nonvolatile semiconductor memory encompassing a plurality of cell columns, each of the cell columns embraces serially connected plural memory cells, the cell columns being arranged very close to each other; and a fabrication method thereof.
2. Description of the Related Art
In recent years, usage of an alumina (Al2O3) film has been proposed for the material of an inter-electrode dielectric, which insulates a first conductive layer (a floating gate electrode) from a second conductive layer (a control gate electrode) as disclosed in “Symposium on VLSI Technology Digest of Technical Papers”, 1997, p. 117. For the double-polysilicon architecture encompassing a polysilicon floating gate electrode and a polysilicon control gate electrode, the inter-electrode dielectric is called “an interpoly dielectric”. The alumina film allows a decreased area of the inter-electrode dielectric and is a suitable material for miniaturized cells since it has a higher dielectric constant than that of the conventional ONO film, which is a triple layer film embracing a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), and a silicon oxide film (SiO2 film). For a similar reason, a high dielectric constant oxide film such as a tantalum oxide film (Ta2O5 film), a zirconium oxide film (ZrO2 film), and a hafnium oxide film (HfO2 film), and doped insulating films are candidates for the material for inter-electrode dielectrics. The doped insulating films are these high dielectric constant oxide films, which are doped with impurity atoms. However, leakage currents, which are impermissible in non-volatile memory, flow through these high dielectric constant insulating films when a certain electric field is applied thereto. Therefore, decreasing the leakage current that flows through the insulating film by postannealing a high dielectric constant insulating film under an oxidizing ambient such as oxygen radical so as to improve its characteristics after deposition thereof is necessary. However, when using as the inter-electrode dielectric, this annealing for improvement in characteristics results in forming a low dielectric constant silicon oxide film on the interface between the first conductive layer and the high dielectric constant insulating film, thereby decreasing the effective dielectric constant for the inter-electrode dielectric. Therefore, the introduction of the high dielectric constant insulating film does not provide an advantage.
It is well known that a silicon nitride film (Si3N4) is formed on the underlayer of the high dielectric constant insulating film so as to avoid forming a silicon oxide film during annealing for the film characteristic improvement. FIG. 1 shows a schematic cross sectional view cut along the length of word lines of a memory cell transistor formed using this earlier technique. Multiple first conductive layers (floating electrodes) 3 are arranged close to each other on a semiconductor substrate (silicon substrate) 1 via a tunnel insulating film, which becomes a cell site gate insulator 2. Each of device isolation films 4 is buried between each first conductive layer. Moreover, a part of the side surfaces and the top surface of the respective first conductive layers 3, and the top surface of the respective device isolation films 4 are covered with a second conductive layer (control gate electrodes) 7 and a complex inter-electrode dielectric, which is made from a lower inter-electrode dielectric (Si3N4 film) 5 and an upper inter-electrode dielectric (Al2O3 film) 6.
However, in the cell structure of FIG. 1, the first conductive layers 3, which are arranged close to each other and partitioned by the device isolation films 4, are connected by the lower inter-electrode dielectric 5. Since the silicon nitride film used as the lower inter-electrode dielectric 5 includes many electron trap levels, a very small part of the electric charge accumulated in one of the first conductive layers 3 flows down to the other of the first conductive layers 3 via the silicon nitride film. The smaller the memory size becomes, the larger the cell threshold voltage change due to such an electric charge migration. Moreover, since nonvolatile memory has to assure ten years of electric charge retention, fabricating miniaturized memory cells is particularly difficult.
It should be noted that this problem is not limited to only the case of a high dielectric constant insulating film being used as the complex inter-electrode dielectrics 5 and 6. Similar problems occur even when the conventional ONO films are used; more specifically, they occur even when a silicon nitride film is formed on the underlayer of an ONO film so as to prevent, for example, decrease of capacitance of the inter-electrode dielectric due to bird's beak oxidation that occurs when forming an electrode sidewall film in the cell region.
In addition, similar problems occur when there is a thin silicon oxide film such as a natural oxide film at the interface of the lower inter-electrode dielectric (Si3N4 film) 5 and the first conductive layers (floating gate electrodes) 3, which are formed on the underlayer of the upper inter-electrode dielectric 6, and even when the underlayer silicon oxide film of the ONO film is thin. In other words, if the silicon oxide film between the first conductive layers 3 and the silicon nitride film is thin enough for the electric charge to easily penetrate, variations in the cell threshold voltage occur due to the electric charge migration between first conductive layers (floating gate electrodes) arranged close to each other.
A memory cell transistor as shown in FIG. 2 has been proposed as a measure for avoiding such problems as disclosed in Japanese Patent Application Laid-open No. 2001-168306. The lower inter-electrode dielectrics 5 for memory cells arranged close to each other and partitioned by the device isolation films 4 have a structure divided by slits 9 on the device isolation films 4, whereby electric charge migration between the first conductive layers 3 is prevented. In other words, in the cell structure shown in FIG. 2, the lower inter-electrode dielectrics 5 for the memory cells arranged close to each other and partitioned by the device isolation films 4 are divided by the slits 9 on the device isolation films 4 so as to prevent electric charge migration between the first conductive layers (floating gate electrodes) 3. In addition, each slit 9 has a part of the second conductive layer (control gate electrodes) 7 embedded therewithin.
However, with the structure shown in FIG. 2 where the insulation between the first conductive layers 3 and the second conductive layer 7 is provided by the device isolation films 4 sandwiched therebetween via the slits 9, since fine and precise positioning of the locations for and forming the slits 9 is difficult, the insulation between the first conductive layers 3 and the second conductive layer 7 cannot be provided for miniaturized memory cells. Thus, problems of weakening data retention capability due to charge leakages and an increasing percentage of short circuit failures occur.
In addition, since a resist film is directly coated onto the surfaces of the inter-electrode dielectrics 5 when processing the slits, the quality of the inter-electrode dielectrics 5 deteriorates. In the case of making the inter-electrode dielectrics 5 as thin insulating films, there is a problem of weakening data retention capability due to electric charge leakage from the first conductive layers (floating gate electrodes) 3 to the second conductive layer (control gate electrodes) 7.